A significant challenge in the design of off-chip driver circuits is to reduce the level of electromagnetic interference by preventing an output pad from being overdriven. When fast rise or fall time pulses are impressed on a chip output pad by excessive output drive levels, electromagnetic interference is radiated. Such excessive levels also create ground and power supply "bounce".
The adjustment of output pad drive current levels must take into account a number of real-world problems. Process variations experienced during chip production may result in changes in conduction channel length, carrier mobility, conduction threshold, oxide thickness, etc. Each process variation can cause a variation in a circuit's output drive. Power supply changes may alter voltage supply values by up to 20%. Temperature variations affect mobility and other semiconductor parameters. Together, process, temperature and voltage variations (hereafter referred to as "PVT") act to cause substantial variation in output rise and fall times.
Another variable parameter requiring output drive adjustment is the load capacitance connected to a chip's output pad. So long as a network interconnected with a chip pad is constant, the load capacitance seen from the pad remains constant and no adjustment is needed. However, many systems are field-configurable and enable circuit boards to be either replaced, augmented, or modified. Each of those actions results in a change in network load capacitance (as seen from a chip pad). Similarly, interconnection circuitry between a chip and the remaining network may also be subject to change, further modifying load capacitance.
Due to the fact that all of the above parameters interact to affect a chip's output electrical characteristics, circuit designers have over-designed output current drivers so that their output currents accommodated the worst case situation. Such designs resulted in excessively large output currents and excessive EMI levels. Additional packaging costs thus had to be incurred to implement added shielding and other EMI prevention techniques.
Another problem created by excessively driven rise and fall times is that signal undershoot and overshoot can result and damage connected circuit inputs, if too severe. Signal under and overshoot can also cause incorrect logic levels due to the "ringing" exceeding a logic level threshold. This ringing is referred to as ground or supply bounce.
PVT variations not only affect output drive currents but also other on-chip signal characteristics such as signal delays. Various prior art references have attempted to adjust circuit parameters in accordance with sensed PVT manifestations. One such system is described by Cox et al. in "VLSI Performance Compensation for Off-Chip Drivers and Clock Generation", IEEE 1989 Custom Integrated Circuits Conference (1989) pp. 14.3.1-14.3.4. Cox et al. employed a long string of inverters as a tapped delay line. By comparing signal propagation through the inverters against a constant frequency clock signal, chip time delays could be determined and signal propagation adjusted so as to prevent skew. Cox et al. also indicated that a number of parallel connected stages in an output driver could be modified to maintain a nearly constant output signal characteristic when "slow" circuit conditions prevailed. Conversely, the number of parallel-connected output drivers were reduced under "fast" circuit conditions to reduce output drive currents. Cox et al. did not take into account any affects resulting from changes in output load capacitance. U.S. Pat. No. 4,939,989 to Cox et al. discloses a similar system to that aforedescribed.
A variable current output driver circuit is disclosed by Kalter et al. in "A 50-ns 16-Mb DRAM with a 10-ns Data Rate and On-Chip ECC" IEEE Journal of Solid State Circuits, Vol. 25, No. 5, October 1990, pp. 1118-1127. At pages 1124-1125, Kalter et al. disclose a rate-control, off-chip driver wherein an analog potential is derived from continuously sampled output rise or fall times. The circuit requires continuous outputs to enable development of the controlling analog potential. Furthermore, the control circuit is, itself, subject to PVT variations.
Dorler et al. in U.S. Pat. No. 4,383,216 disclose an on-chip delay regulator circuit which was used to minimize chip-to-chip circuit speed differences caused by PVT variations. Changes in a periodic reference signal from a phase locked loop were employed to create an error signal which changed the applied power to the on-chip circuits. This action caused gate delays to be either increased or decreased, as necessary, to maintain a relatively constant circuit speed.
An article by Kumar in the July, 1990 issue of ASiC Technology News, pages 20-21, briefly describes a number of techniques used by designers to reduce electrical noise that occurs as a result of increased switching speeds. Kumar indicated that others have employed bi-level drivers wherein either a standard full strength drive output or a reduced drive, low noise, output is available. He indicated that the selection of drive level could be made at the time of fabrication or could be register-programmable. No indication is provided by Kumar as to a technique for enabling such drive current adjustment. Bell et al. in U.S. Pat. No. 4,494,021 employ an automatic frequency control loop wherein a voltage controlled oscillator's frequency was regulated to be equal to that of a reference frequency. The control voltage for adjusting the oscillator frequency was also employed to regulate stage-to-stage delay in the circuit.
A number of references describe the use of analog voltages to control circuit changes which occur as a result of PVT variations. See "A 300k-Circuit ASIC Logic Family" Petrovick, Jr et al 1990 IEEE International Solid-State Circuits Conference, pages 88-89, (1990); King et al., "Delay and Power Tolerance Regulator For FET Logic" IBM Technical Disclosure Bulletin, Vol. 23, No. 4, September 1980, pp. 1305-1306; Kilmer, "Process-Independent Delay Driver" IBM Technical Disclosure Bulletin, Vol. 23, No. 9, February 1981, pp. 4187-4188; and the following U.S. Pat. No. 4,473,762 to Iwahashi et al., U.S. Pat. No. 4,815,113 to Ludwig et al., U.S. Pat. No. 4,623,805 to Flora et al., U.S. Pat. No. 4,641,048 to Pollock, U.S. Pat. No. 4,684,897 to Richards et al., U.S. Pat. No. 4,691,124 to Ledzius et al., and U.S. Pat. No. 4,818,901 to Young et al.
Accordingly, it is an object of this invention to provide an adaptable output drive circuit for a chip which is responsive to both PVT parameter modifications and load capacitance changes.
It is another object of this invention to provide a programmable output drive circuit whose performance may be altered periodically during chip operation.
It is yet another object of this invention to provide a programmable output drive circuit exhibiting minimized EMI.
It is still another object of this invention to provide a programmable output drive circuit which exhibits lessened power supply "bounce" characteristics.